Optimized Model of Radix-4 Booth Multiplier in VHDL

This paper describes optimized radix-4 booth multiplier algorithm for multiplication of two binary numbers on VHDL device. Radix-4 Booth’s algorithm is presented as an alternate solution of basic binary multiplication, which can help in reducing the number of partial products by a factor of 2. Radix-4 Booth’s multiplier alters the way of addition of partial products thereby using Carry-Save-Adders. Simulation result shows the minimization in operational time and power. Motivation of the analysis is to encourage the amateur researcher in the field of radix-4 booth multiplier. So that they can understand easily the concept of radix-4 booth multiplier and can contribute in developing more efficient booth multiplier algorithm. This will benefit interested researcher to carry out further work in this thrust area of research. Keywords— Binary number, Booth’s algorithm, Radix-4 Booth’s algorithm, VHDL.